1. Technical Field
The present invention relates to hybrid-orientation substrate structures, and more specifically, to hybrid-orientation substrate structures with discharge damage prevention features.
2. Related Art
A typical hybrid-orientation substrate may include two different silicon regions (namely first and second silicon regions) having different lattice orientations on the same substrate. For example, the first silicon region may comprise <100> lattice orientation silicon (or in short, <100> silicon), whereas the second silicon region may comprise <110> lattice orientation silicon (or in short, <110> silicon). In one case, the first region may be on and in direct physical contact with the substrate, whereas the second region may be on the same substrate but physically and electrically separated from the first silicon region and the substrate by a dielectric region. Usually, N channel field effect transistors (NFETs) are formed on the first region (comprising <100> silicon), whereas P channel FETs (PFETs) are formed on the second region (comprising <110> silicon). The reason is that NFETs operate faster when formed on <100> silicon than on <110> silicon, while PFETs operate faster when formed on <110> silicon than on <100> silicon.
During the fabrication of the FETs and other structures (e.g., interconnect lines, etc.) on the typical hybrid-orientation substrate, plasma may be involved in some fabrication steps. For example, reactive ion etching (RIE), plasma enhanced chemical vapor deposition (PECVD), metal deposition in a sputter plasma tool, etc. are some example processes that involve the use of a plasma (hereafter, referred to as plasma processes). During these plasma processes, different nodes of the FETs may have different voltage potentials that may result in current discharge that may cause damage to the FETs (namely, discharge damage).
Therefore, there is a need for a hybrid-orientation substrate structure (and a method for forming the same) with discharge prevention features.